Application Specific Integrated Circuits (ASICs) are designed using a variety of Computer Aided Design (CAD) tools. The development of ASICs with CAD tools is often referred to as Electronic Design Automation (EDA).
Known CAD tools include datapath synthesis tools, datapath compilation tools, chip estimation tools and HDL generation tools. A datapath synthesis tool processes a high-level characterization of a datapath circuit into a specific circuit. More particularly, a datapath synthesis tool synthesizes a specified circuit using a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL characterization of the circuit provides a Register Transfer Level (RT-level) description of an ASIC and a set of design constraints. The datapath synthesis tool then tries to map the HDL circuit description, within the design constraints, into a netlist. A netlist is comprised of a list of circuit components and the interconnections between the components. The circuit components are obtained from a datapath cell library.
An HDL generation tool converts a schematic netlist into an HDL description of the circuit (which may include RAMs, ROMs, datapath cells and other standard circuit cells). The HDL description may then be used in simulation operations.
Another known CAD tool is a datapath compilation tool. A high-performance ASIC typically includes a datapath that computes the arithmetic and logic functions of the ASIC. The central processing unit (CPU) of a computer and the processing pan of a digital signal processor (DSP) are examples of datapaths. A datapath design is a network of datapath cells, such as multipliers, adders, ALUs, multiplexers and register-files. These cells have regular structures that are efficiently implemented in a bit-slice fashion. This bit-slice structure is obtained by "tiling" together a variety of "leaf cells". That is, a number of logical gates ("leaf cells") are grouped ("tiled") together to achieve a bit-slice structure.
Prior art datapath compilation tools rely upon bitwidth when calculating relevant power requirements, This technique is adequate for the simple non-parameterized datapath cells typically used in the past. However, the technique cannot model complex cells that are now available in datapath libraries. Thus, it would be desirable to provide a datapath compilation tool which enables more sophisticated power consumption calculations that are based upon such factors as frequency, activity rate, and voltage derating values.
Another problem with prior art datapath compilation tools is that physical information regarding the datapath is only available after a time-consuming and computationally expensive compiling operation. This approach yields physical information for a complete datapath design. It is frequently desirable to obtain physical information for datapath functions without relying upon a time-consuming and computationally expensive compilation of an entire datapath.
A chip estimator, also known as a chip estimation tool, is another tool that is used in an electronic design automation process. As suggested by its name, a chip estimator provides general information regarding such issues as how big a circuit will be, what its power dissipation will be, whether the design should be partitioned into two chips, the type of package to be used, and other issues considered during a feasibility assessment of a design.
The chip estimator can be commanded to generate estimates for each instance of a cell or to generate estimates for an entire chip. Each cell instance can hold parameters called attributes, such as the number of shifts for a barrel shifter or the word size for a multiplier. These parameters are used to make individual estimates associated with a chip design.